1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor memory devices having a mirroring function of handling a plurality of bits of memory cells as a 1-bit, pseudo memory cell in accessing data.
2. Description of the Background Art
FIG. 11 schematically shows a configuration of a portion related to data of one bit of a conventional semiconductor memory device. In FIG. 11, the semiconductor memory device includes: memory sub arrays MSA0-MSAn each having a plurality of memory cells arranged in rows and columns; row decoders RD0-RDn provided corresponding to memory sub arrays MSA0-MSAn, respectively, each for selecting a row of a corresponding memory sub array; a column decoder CD provided commonly to memory sub arrays MSA0-MSAn to select a column in memory sub arrays MSA0-MSAn; internal IO line pairs IOP0-IOPn provided corresponding to memory sub arrays MSA-MSAn, respectively, and each coupled with a column selected by column decoder CD of a corresponding memory sub array; preamplifiers PAM0-PAMn provided corresponding to internal line IO line pairs IOP0-IOPn, respectively, and selectively activated to amplify data on their corresponding internal IO line pairs IOP0-IOPn and transmit the amplified data to an internal data line pair DBP; and a main amplifier MAP for amplifying the data on internal data line pair DBP and externally outputting the amplified data.
Memory array MA shown in FIG. 11 configures one IO block and externally communicates data of one bit.
Preamplifiers PAM0-PAMn are selectively activated according to an address bit specifying a memory sub array. Internal IO line pairs IOP0-IOPn and internal data line pair DBP each transfer data of one bit.
FIG. 12 schematically shows a configuration of memory sub arrays MSA0-MSAn shown in FIG. 11. Since these memory sub arrays MSA0-MSAn are identical in configuration, FIG. 12 shows a configuration of one memory sub array MSAi representatively, wherein i=0 to n.
In FIG. 12, memory sub array MSAi includes: a plurality of memory cells MCs arranged in rows and columns; a bit line pair BLP (BLP0-BLP3) arranged corresponding to each column of memory cells MCs; a word line WL (WL0-WLm) arranged corresponding to each row of memory cells MCs; a sense refresh amplifiers SA (SA-SA3) provided corresponding to bit line pairs BLP and each activated in response to a signal on sense drive lines S2P and S2N; a sense amplifier driver SAD for driving sense drive lines S2P and S2N in response to sense amplifier activation signals ZSOP and SON; and a column select gates CG (CG0-CG3) provided corresponding to bit line pairs BLP (BLP0-BLP3), and each operative in response to a column select signal CSL (CSL0-CSL3) to connect a corresponding bit line pair to internal IO line pair IOP.
Although memory sub array MSAi has a plurality of columns of memory cells arranged therein, FIG. 12 representatively shows memory cells arranged in four columns.
A memory cell MC includes a capacitor MS for storing information, and an access transistor (an N-channel MOS (insulated gate type) transistor) MT operative in response to a signal on a corresponding word line WL to connect capacitor MS to a corresponding bit line.
Bit line pair BLP includes a bit line BL (BL0-BL3) and a bit line ZBL (ZBL0-ZBL3). Memory cell MC is arranged corresponding to a crossing of one of bit lines BL and ZBL of a corresponding bit line pair BLP and a corresponding word line WL.
Sense refresh amplifier SA includes a P sense amplifier configured of cross-coupled P-channel MOS transistors, and cross-coupled N-channel MOS transistors. When sense drive line S2P attains a power supply voltage level, the P sense amplifier is activated to drive, to the power supply voltage level, a bit line at a higher potential in a corresponding bit line pair. When sense drive line S2N is driven low, the N sense amplifier is activated to drive, to a low level of a ground voltage level for example, a bit line at a lower potential in the corresponding bit line pair.
Sense amplifier driver SAD drives sense drive lines S2N and S2P to a low level and a high level, respectively, in response to a sense start signal SA and a restore signal GZOP to activate sense refresh amplifier SA (SA0-SA3).
Column select gate CG (CG0-CG3) includes transfer gates TX connecting bit lines BL and ZBL of a corresponding bit line pair BLP to IO lines IO and ZIO of internal IO line pair IOP in response to a corresponding column select signal. In response to column select signal CSL (one of CSL0-CSL3), a column is selected in each memory sub array and bit line pair BLP of a corresponding column is connected to a corresponding internal IO line pair IOP. A data read operation for memory sub arrays shown in the FIG. 12 will now be described with reference to a signal waveform diagram shown in FIG. 13.
In a standby state, a bit line precharge/equalization circuit (not shown) precharges and equalizes each bit line BL and ZBL to a voltage level of an intermediate voltage, which is equal to Vcc/2. In the following description, bit lines BL and ZBL will be referred to as generically indicating bit lines BL0-BL3 and ZBL0-ZBL3 shown in FIG. 12. The bit line precharge/equalization circuit is provided for each bit line pair and it is activated when a bit line precharge/equalization instructing signal BLEQ is at a high level.
In the standby state, internal IO lines ZIO and IO are also precharged to the power supply voltage Vcc level.
When an active cycle starts, a row decoder is first activated to drive a word line WL corresponding to an addressed row to a boosted voltage Vpp level of a selected state. When word line WL is driven to the selected state, a memory cell connected to the selected word line WL has its storage data read on a corresponding bit line BL or ZBL. FIG. 13 represents a signal waveform when high-level data is read on bit line BL.
Then, when a predetermined period of time elapses, sense start signal SON is activated, sense amplifier driver SAD drives sense drive line S2N to a low level. Responsively, sense refresh amplifier SA (generically referring to SA0-SA3 unless otherwise mentioned) is activated and bit line ZBL at a low potential level is discharged to a ground voltage level.
Restore signal ZSOP is then driven to attain a low level and sense drive line S2P is responsibly driven to attain the power supply voltage Vcc level. Thus, bit line BL is driven to attain the power supply voltage level. Sense refresh amplifier SA has a configuration of a flip-flop configured of cross-coupled P-channel MOS transistors and cross-coupled N-channel MOS transistors and it has a latch function. After this restoring completes, bit lines BL and ZBL is held by self refresh amplifier SA at a high level and a low level depending on the data of the selected memory cell.
In accessing a column, in response to a column address signal, a column select signal CSL for selecting an addressed column is driven into a selected state by column decoder CD. A corresponding column select gate CG is rendered conducts and bit line pair BLP corresponding to this column select gate is connected to internal IO line pair IOP. Internal IO lines IO and ZIO are clamped in reading data to the power supply voltage Vcc level, and internal IO lines IO and ZIO have their respective potentials varying with the data latched by the sense amplifier. In FIG. 13 bit line ZBL is at a low level, and internal IO line ZIO attains a voltage level lower than that of internal IO line IO.
A signal of a small amplitude on the internal I/O line is amplified by preamplifier PAM to be a signal of a CMOS level and the amplified signal is transmitted through internal data line pair DBP. When a column select operation completes, column select signal CSL is driven low. The signal on internal data line pair DBP is amplified by the main amplifier at a predetermined timing and then externally output.
When one memory cycle completes, word line WL in the selected state is driven into a non-selected state and the access transistor MT of the selected memory cell turns off. Then sense start signal SON and restore signal ZSOP are driven to the low level and the high level, respectively, and thus inactivated, and bit lines BL and ZBL enter a floating state. Then bit line precharge/equalization instructing signal BLEQ is driven high to be an active state, and bit lines BL and ZBL are precharged and equalized by a bit line precharge/equalization circuit (not shown) to attain an intermediate voltage level.
FIG. 14 schematically shows a configuration of a circuit from internal data line pair IOP to a data input/output terminal. FIG. 14 representatively shows a configuration provided corresponding to three internal IO line pairs IOP0-IOP2. Internal IO line pairs IOP0-IOP2 are provided in parallel corresponding to a 1-bit data input/output terminal and they are selectively coupled with internal data line pair DBP.
Corresponding to these internal data line pairs IOP0-IOP2, preamplifiers PAM0-PAM2 are provided, respectively. When select signals SEL0-SE02 are activated, preamplifiers PAM-PAM2 are activated in response to a preamplifier enable signal (not shown) to amplify complementary signals on corresponding internal IO line pairs IOP0-IOP2 and transmits the amplified signals to internal data line pair DBP. Corresponding to IO line pairs IOP0-IOP2, write drivers WDR0-WDR2 are provided, respectively. When select signals SEL0-SEL2 are selected and activated, write drivers WDR0-WDR2 are enabled in response to a write driver enable signal (not shown) to generate internal write data from signals on internal data line pair DBP and transmit the generated data to a corresponding internal IO line pair. Select signals SEL0-SEL2, . . . are activated through decoding of an address bit specifying a memory sub array.
Internal data line pair DBP is provided with a data latch circuit DLK entering a through state, in response to a read data latch instruction signal RDL, for a predetermined period of time and enter a latching state for the period of time excluding the predetermined period of time. A signal output from data latch circuit DLK is transmitted to main amplifier MAP. Reference will now be made to a signal waveform shown in FIG. 15 to describe an operation in reading data of the configuration of FIG. 14.
When column select signal CSL is driven high, data latched by a sense refresh amplifier that is arranged for a selected column of a corresponding memory sub array, is transmitted to each of internal IO line pairs IOP0-IOP2 (IO lines IO and ZIO).
When the potential of a signal on an internal IO line is sufficiently developed, a preamplifier enable signal PAE is activated and preamplifier PAM selected by select signals SEL0-SEL2 is activated to amplify complementary data on a corresponding internal IO line pair.
When preamplifier enable signal PAE is activated, data latch instructing signal RDL attains a low level for a predetermined period of time and data latch circuit DLK enters a through state to pass and also latch the data on internal data line pair DBP transmitted by a selected preamplifier PAM. Then, in response to a signal transmitted by data latch circuit DLK main amplifier MAP drives a data input/output terminal and external read data DQ is generated.
Main amplifier MAP drives the data terminal in three values in response to complementary signals on internal data line pair DBP that are transmitted via data latch circuit DLK. Specifically, when internal data lines DB and ZDB are both set to a high level, the data input/output terminal outputs read data DQ in a high impedance state (Hi-Z). When internal data lines ZDB and DB are at a low level and a high level, read data DQ goes high. When internal data lines ZDB and DB are at a high level and a low level, respectively, read data DQ is driven low.
Data latch circuit DLK and main amplifier MAP are reset after a column access completes. For example, they are reset by an address transition detection signal ATD or inactivation of a column address strobe signal/CAS.
An amplitude of internal IO line pair IOP is determined by low-level data latched by sense refresh amplifier SA, and the signals on internal data lines DB and ZDB are driven by preamplifier PAM to the CMOS level signal.
As described above, in a dynamic random access memory (DRAM), an electric charge stored in a capacitor MS, is read on a corresponding bit line and a variation in voltage attributed to the read electric charge is amplified by a sense refresh amplifier and then transmitted to an internal IO line pair. This variance xcex94V in voltage on a bit line attributed to data of a memory cell read on the bit line, is determined depending on the amount of electric charge accumulated in a memory cell capacitor, as given typically in the following expression:
xcex94V=(Vcc/2)xc2x7{1/(1+Cb/Cs)}, 
where Cs represents a capacitance of memory cell capacitor Ms and Cb represents a stray capacitance of a bit line.
In recent years, as sub-micro-fabrication techniques have advanced, a memory cell capacitor is reduced in capacitance value and a bit line accordingly receives a small voltage change (read voltage), and memory cell data is more likely read erroneously. If a 1-bit memory cell is defective and cannot be repaired, the memory device of interest is determined to be defective. To eliminate such a possibility and accurately read memory cell data, data is mirrored. Conventionally, data is mirrored by storing single data at a plurality of bit locations and handling these multiple bits in a pseudo manner as one bit to repair a defective bit in a magnetic disc device, for example, to ensure that data is accurately recorded/reproduced.
FIG. 16 shows a configuration of a conventional memory array with such a mirroring technique applied. In FIG. 16, word lines WL0-WLn are connected to row decoder RD. Word line WL0 is coupled with three branch word lines WL01-WL3, and word line WLn is also coupled with three branch word lines WLn1-WLn3. A row of memory cells is connected to each of branch word lines WL01-WL03 and WLn1-WLn3 in a memory sub array.
A bit line has a configuration similar to that shown in FIG. 12, and a sense refresh amplifier SA and a bit line precharge/equalization circuit P/E are provided corresponding to each bit line pair. Bit line precharge/equalization circuit P/E includes precharging N-channel MOS transistors Q0 and Q1 responsive to a bit line precharge/equalization signal BLEQ and an equalizing N-channel MOS transistor Q2 responsive to the bit line precharge/equalization signal BLEQ. When bit line precharge/equalization indicating signal BLEQ is activated, N-channel MOS transistors Q0 and Q1 turn on to transmit a precharge voltage VBL to bit lines ZBL and BL, respectively, and N-channel MOS transistor Q2 also turns on to electrically short-circuit bit lines BL and ZBL.
Sense refresh amplifier SA includes cross-coupled N-channel MOS transistors NQ0 and NQ1 and cross-coupled P-channel MOS transistors PQ0 and PQ1. N-channel MOS transistors NQ0 and NQ1 have their source coupled with sense drive line S2N and P-channel MOS transistors PQ0 and PQ1 have their source coupled with sense drive line S2P. Column select gate CG includes transfer gates TX connecting bit lines ZBL and BL to internal IO lines ZIO and IO in response to a column select signal CSL.
For each of word lines WL0-WLn, memory cells connected to corresponding branch word lines Wli-Wli3 are connected to a common bit line. In FIG. 16, memory cells MC1-MC3 are arranged at crossings of the branch word lines WL01-WL03, and bit line ZBL and memory cells MC1-MC3 are arranged at crossings of the branch word lines WLn1-WLn3 and bit line BL. These memory cells of three bits simultaneously selected will be referred to as a xe2x80x9cmirror memory cellsxe2x80x9d hereinafter.
When row decoder RD selects one word line WLi, memory cells MC1-MC3 of three bits simultaneously transmit stored data on bit line BL or ZBL. In a memory cell arrangement using this mirroring technique also, bit line potential variation is the same as that shown in FIG. 13. Now, a description will now be made specifically of a bit line read voltage when the mirroring technique is used.
As shown in FIG. 17, memory cells MC1-MC3 are arranged corresponding to crossings of word line WL and bit line BL for the sake of description. For memory cells MC1-MC3, their respective storage nodes have voltages Vsn1, Vsn2 and Vsn3, and their memory capacitors each have a capacitance value Cs. These storage node voltages Vsn1-Vsn3 are at the power supply voltage Vcc level in storing high-level data and at a ground voltage (0V) level in storing low-level data. The memory cell capacitor has a cell plate receiving a voltage Vcp, which is equal to Vcc/2.
For bit line BL, there exists stray capacitance Cb. Furthermore, bit line BL is precharged to the intermediate voltage VBL, which is equal to Vcc/2.
As shown in FIG. 17B, when memory cells MC1-MC3 are in a non-selected state, their respective access transistors turn off and the capacitors are disconnected from the corresponding bit line BL. The total amount QA of electric charge stored in the memory capacitors and that stored in the stray capacitance of a bit line in this non-selected state, can be represented in the following expression:
QA=Csxc2x7(Vsn1xe2x88x92Vcp)+Csxc2x7(Vsn2xe2x88x92Vcp)+Csxc2x7(Vsn3xe2x88x92Vcp)+Cbxc2x7VBL, 
where storage node voltages Vsn1-Vsn3 each are either power supply voltage Vcc or ground voltage 0V.
Then, as shown in FIG. 17C, when word line WL is selected, these memory cells have their capacitors connected to the corresponding bit line and electric charge moves. Since a memory cell capacitor and the stray capacitance of the bit line are connected in parallel to bit line BL, electric charge QB currently stored in the memory cell capacitors is represented by the following equation:
QB=3xc2x7Cs(Vsnxe2x88x92Vcp)+Cbxc2x7VB. 
Since the storage node voltage Vsn of each of the memory capacitors is equal to an electrode voltage VB of the bit line stray capacitance Cb, i.e., Vsn=VB, the following expression can be obtained:
QB=3xc2x7Cs(Vsnxe2x88x92Vcp)+Cbxc2x7Vsn. 
Thus, when the memory cells normally store data, they store data at the same logic level and the following expression can be established:
Vsn1=Vsn2=Vsn3=Vsn0. 
Therefore, from the principle of conservation of electric charge, QA is equal to QB, and the following expression can be obtained:
3xc2x7Csxc2x7Vsn0+Cbxc2x7VBL=3xc2x7Csxc2x7Vsn+Cbxc2x7Vsn. 
Thus, when memory cells are selected, a bit line voltage variation xcex94Vb, which is equal to Vsnxe2x88x92VBL, is represented by the following expression:                               Δ          ⁢                      xe2x80x83                    ⁢          Vb                =                  Vsn          -          VBL                                        =                  3          ·          Cs          ·                                    (                              Vsn0                -                VBL                            )                        /                                          (                                                      3                    ⁢                    Cs                                    +                  Cb                                )                            .                                          
Thus, as shown in FIG. 17D, if intermediate voltage VBL is at an intermediate value of a power supply voltage, i.e., Vcc/2, a bit line receives a read voltage xcex94V=|xcex94Vb| equal to (Vcc/2)/(1+Cb/3Cs) in both reading high-level data and reading low-level data.
If one of memory cells MC1-MC3 has its storage data destroyed and storage node voltages Vsn1 and Vsn2 are equal to a voltage VsnA and storage node voltage Vsn3 is equal to a voltage VsnB in a standby state for the sake of description. In the standby state, the total amount QA of electric charge stored in the memory cell capacitors and a bit line stray capacitance can be represented by the following equation:
QA=2xc2x7Csxc2x7(VsnAxe2x88x92Vcp)+Csxc2x7(VsnBxe2x88x92Vcp)+Cbxc2x7VBL, 
where storage node voltages VsnA and VsnB are at different logic levels.
The total electric charge QB stored in the capacitors connected to a bit line after a word line is selected, can be represented similarly as in a normal state, as follows:
QB=3xc2x7Csxc2x7(Vsnxe2x88x92Vcp)+Cbxc2x7Vsn. 
Therefore, a bit line voltage variance xcex94Vb in reading data can be represented by the following equation:                               Δ          ⁢                      xe2x80x83                    ⁢          Vb                =                  Vsn          -          VBL                                        =                  2          ·                                    (                              VsnA                +                VsnB                -                                  3                  ·                  VBL                                            )                        /                                          (                                  3                  +                                      Cb                    /                    Cs                                                  )                            .                                          
If one bit is defective, a bit line voltage has two different values depending on the following two conditions, as shown in FIG. 17E:
If VsnA=Vcc and VsnB=0V, then xcex94Vb=(xc2xd)xc2x7Vcc/(3+Cb/Cs).
If VsnA=0V and VsnB=Vcc, then xcex94Vb=(xe2x88x92xc2xd)xc2x7Vcc/(3+Cb/Cs).
Thus, in mirror memory cells storing data of one bit, the memory cells of three bits have the same data written therein, and in a normal read operation electric charge three times greater than in a conventional case is transmitted on an associated bit line. This, bit line voltage level is determined by a so-called xe2x80x9cprinciple of decision by majorityxe2x80x9d depending on electric charge stored in memory cell capacitors.
If a memory cell of one bit in the mirror memory cells has the storage data inverted due to a soft error or the like, the remaining two bits compensate for the inverted data of one bit and, electric charge corresponding to correct data of a 1-bit memory cell in total is transmitted to a bit line, similarly as in a conventional case. Then, by rewriting data via a sense refresh amplifier, correct data can be written back. After data is read, correct data can be stored in all the mirror memory cells of the three bits. Since data is read according to the principle of decision by majority as described above, it is desirable to form the mirror memory cells by an odd number of bits of memory cells.
FIG. 18A shows another configuration of an array of a semiconductor memory device using a conventional mirroring technique. In the array configuration shown in FIG. 18A, word lines WL0-WLn from a row decoder are each divided into two branch word lines. Specifically, word line WL0 branches into branch word lines WL01 and WL02 and word line WLn branches into branch word lines WLn1 and WLn2. For these sets of branch word lines, memory cells are arranged such that memory cell data are read on bit lines ZBL and BL when a corresponding branch word lines are selected. More specifically, mirror memory cells include a memory cell MCb connected to bit line BL and a memory cell MCa connected to bit line ZBL. The remaining of the configuration of the bit line peripheral circuit is identical to the configuration shown in FIG. 16.
In the array arrangement in FIG. 18A, when a word line is selected, memory cell data are read on bit lines BL and ZBL. Sense refresh amplifier SA differentially amplifies potentials of the signals on bit lines BL and ZBL, and mirror memory cells MCa and MCb constantly store complementary data to each other. Thus, as shown in FIG. 18B, when a word line is selected, bit lines BL and ZBL have their respective voltages both varied from the bit line precharge voltage, and the read voltage can equivalently be increased to prevent an erroneous data read operation due to data held by a defective memory cell.
Furthermore, in the mirror memory cell configuration as shown in FIG. 18, if a defect such as a micro short circuit exists between branch word lines, driving these branch word lines by row decoder RD simultaneously to a selected state can drive the word lines with an inter-word line short circuit to a selected state, and thus a defect of such an inter-word line short circuit can be repaired.
In the arrangement shown in FIG. 18A, mirror memory cells are configured of two memory cells MCa and MCb. Thus, if the data stored in a memory cell of one bit is inverted, read data varying in the same direction are transmitted on bit lines BL and ZBL and data cannot be read accurately.
As a large scale integrated circuit (LSI) is micro-fabricated in recent years, a memory cell capacitor is also miniaturized, and accordingly a memory cell can only store a reduced amount of electric charge. It is thus susceptible to a soft error destroying data of a memory cell or data on a bit line. For the mirroring technique shown in FIG. 16, if a memory cell itself has a defect, the error can be corrected according to the principle of decision by majority. However, if a bit line coupling noise or the like destroys a read voltage after data of a memory cell is read on a bit line and before a sense operation starts and a soft error of a bit line mode is caused, the mirror memory cells are configured of memory cells connected to a common bit line, and all bits would cause a soft error and the data destruction cannot be corrected.
Furthermore, as the operating power supply voltage for the memory cell array is lowered and accordingly the read voltage xcex94V read on the bit line is reduced. Therefore, the sensitivity of a self refresh amplifier, the operating margin of the sense fresh amplifier and the like serve as a main factor for data destruction in a read operation. Thus, in a configuration that memory cells of a common bit line are used as mirror memory cells, as shown in FIG. 16, if a bit line coupling noise or the like causes data destruction (read voltage destruction) or a defective operation of a sense refresh amplifier, data cannot be read accurately and the reliability of mirrored data is impaired.
Other types of memory devices also suffer the problem of an erroneous data reading attributed to noise on a bit line. For example, a memory cell of a static random access memory (SRAM) has a flip-flop configuration and stores complementary data. Data reliability needs to be improved against a soft error of a bit line mode attributed to noise on a bit line, rather than a soft error attributed to a defect of a memory cell itself.
FIG. 19 shows an example of a configuration of a conventional memory module. This memory module MM includes memory chips CH0-CH8 corresponding to data bits DQ0-DQ8, respectively. If nine bits of data are stored, one bit, for example, is used for error correction (ECC). However, if the mirror memory cell configuration as shown in FIG. 16 is applied to such a configuration and a parity bit suffers a bit line mode defect, accurate data read and hence accurate parity check cannot be achieved.
Furthermore, in the mirror memory cell arrangement as shown in FIG. 18, if a noise is generated on one bit line and bit lines BL and ZBL of a bit line pair vary bin voltage in the same direction, accurate data read cannot be achieved and data reliability can not be ensured against a bit line mode defect.
An object of the present invention is to provide a semiconductor memory device with improved data reliability.
Another object of the present invention is to provide a semiconductor memory device capable of accurately restoring data in an original memory cell, ensuring an error correction even if a bit line mode defect occurs.
Further object of the present invention is to provide a semiconductor memory device having an improved mirror memory cell configuration.
In accordance with the present invention, a semiconductor memory device includes a plurality of memory cells, a first select circuit for selecting memory cells from the plurality of memory cells and reading the data stored in the selected memory cells in parallel on a first data line, and a second select circuit for coupling the first data lines with a second data line. The second select circuit couples a predetermined number of first data lines of the plurality of the first data lines with a common second data line of the second data lines in parallel.
With mirror memory cells configured by memory cells arranged corresponding to different data lines, if one data line suffers a noise or the like and a data line mode defect such as a bit line mode defect occurs, it is less likely that the remaining data lines will suffer a soft error attributed, for example, to such a noise. Even if such a soft error is caused, data can be read accurately.
Furthermore, restoring allows accurate data to be written in the mirror memory cell suffering the failure.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.